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Features
* * * * * * * * * * * *
Supply Voltage: 8.5V RF Frequency Range: 1400 MHz to 1550 MHz IF Frequency Range: 150 MHz to 250 MHz Enhanced IM3 Rejection Overall Gain Control Range: 30 dB Typically DSB Noise Figure: 10 dB Gain-controlled Amplifier and L-band Mixer Power-down Function for the Analog Part On-chip Gain-control Circuitry On-chip VCO, Typical Frequency 1261.568 MHz Internal VCO Can Be Overdriven by an External LO On-chip Frequency Synthesizer - Fixed LO Divider Factor: 2464 - Nine Selectable Reference Divider Factors: 32, 33, 35, 36, 48, 49, 63, 64, 65 - A Reference Oscillator (Can Be Overdriven by an External Reference Signal) - Tri-state Phase Detector with Programmable Charge Pump - Programmable Deactivation of Tuning Output - Lock-status Indication - Test Interface
L-band Down-converter for DAB Receivers ATR2730 Preliminary
1. Description
The ATR2730 is a monolithically integrated L-band down-converter circuit fabricated with Atmel(R)'s advanced UHF5S technology. This IC covers all functions of an L-band down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control block, a power-save function for the analog part, an L-band oscillator, and a complete frequency synthesizer unit. The frequency synthesizer block consists of a reference oscillator/buffer, a reference divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface, and a control interface.
4903C-DAB-03/07
Figure 1-1.
Block Diagram
TH
17
IF
19
VCC1 VCC3 VCC4 VCC2
3 20 28 9
GND
6, 7, 8, 21, 22, 23, 24
AGC
18 Internal 5V supply voltage for frequency synthesizer Voltage stabilizer 14
U
Analog part 26 25 5 VCO 4 Power save (analog part) Reference counter : Nref RF counter : 2464 Tristate phase detector Bandgap Lock detector
PLCK
RF NRF
20 k 12
TANK VREF
CD
Charge pump 200/300
13 Lock detector Test interface 1 15 16 11 Control interface 10 27 2
PD
PSM
OSCB
OSCE
TI
CI
SI1
SI2
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ATR2730 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning SSO28
PSM SI2 VCC1 VREF TANK GND GND GND VCC2 1 2 3 4 5 6 7 8 9 28 VCC4 27 SI1 26 RF 25 NRF 24 GND 23 GND 22 GND 21 GND 20 VCC3 19 IF 18 AGC 17 TH 16 OSCE 15 OSCB
CI 10 TI 11 CD 12 PD 13 PLCK 14
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Table 2-1.
Pin 1 2 3 4 5 6, 7, 8, 21, 22, 23, 24 9 10 11 12 13 14 15 16 17 18 19 20 25 26 27 28
Pin Description
Symbol PSM SI2 VCC1 VREF TANK GND VCC2 CI TI CD PD PLCK OSCB OSCE TH AGC IF VCC3 NRF RF SI1 VCC4 Function Power save mode Control input Supply voltage VCO Reference pin of VCO Tank pin of VCO Ground Supply voltage PLL Control input Test interface Active filter output Tri-state charge pump output Lock-indication output (open collector) Input of internal oscillator/buffer Output of internal oscillator/buffer Threshold voltage of comparator Charge-pump output of comparator, AGC input for amplifier and mixer Intermediate frequency output Supply voltage RF input (inverted) RF input Control input Supply voltage
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ATR2730 [Preliminary]
3. Functional Description
The ATR2730 is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator, and a frequency synthesizer block. Designed for applications in a DAB receiver, the circuit down-converts incoming L-band signals in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of 190 MHz to 230 MHz, which can be handled by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1-1 on page 2.
3.1
Gain-controlled Amplifier
RF signals applied to the RF input pin are amplified by a gain-controlled amplifier. The complementary pin NRF is not internally blocked; it is recommended to block this pin carefully by an external capacitor. The gain-control voltage is generated by internal gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.
3.2
Gain-controlled Mixer and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about 500 MHz, and then it is fed to the single-ended output pin IF.
3.3
Gain-control Circuitry
The gain-control circuitry measures the signal power, compares it with a certain power level and generates control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in Figure 10-1 on page 14. In order to meet this functionality, the output signal of the buffer amplifier is weakly band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass filtered, and fed to a comparator whose threshold can be defined by an external resistor, RTH, at pin TH. By varying the value of this resistor, a power threshold of about -33 dBm to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below -25 dBm. An appropriate application is shown in Figure 8-1 on page 12. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the AGC pin. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the AGC pin is used to control the gain setting of the gain-controlled amplifier and mixer. The voltage at pin AGC is in the range of 5.75V for maximum gain and 0.3V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the ATR2730 to achieve an extended AGC range. By applying an external voltage to the AGC pin, the internal AGC loop can be overdriven.
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3.4
Voltage-controlled Oscillator
A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this oscillator is shown in Figure 10-2 on page 14. In the application circuits (Figure 10-3 on page 15 and Figure 11-1 on page 16), a ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should be noted that Vref has to be blocked carefully. Figure 11-1 shows a different application where the oscillator is overdriven by an external oscillator. In either case, a DC path at a low impedance must be established between the TANK and VREF pins. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO's frequency on the frequency of a reference oscillator. Figure 9-1 on page 13 shows the typical phase-noise performance of the oscillator in locked state.
3.5
Overall Properties of the Signal Path
The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. With a new AGC concept in the amplifier and mixer, the ATR2730 reaches better intermodulation distances (DIM3) at higher IF-output power levels.
3.6
Power Save Mode
For VPSM > 2V (pin 1) the power consumption in the analog part (gain-controlled amplifier and mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the PLL is not influenced by the power-down mode.
3.7
Frequency Synthesizer
The frequency synthesizer block consists of a reference oscillator, a reference divider, an LO divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface, and a test interface. The control interface is accessed by three control pins, CI, SI1 and SI2. The test interface provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency fVCO of the internal VCO on the frequency fref of the reference signal applied to the input pin OSCB phase-locked loop according to the following equation: fVCO = SF x fref / SFref where: SF = 2464, SFref is the scaling factor of the reference divider according to Table 3-1
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ATR2730 [Preliminary]
Table 3-1. Scaling Factors of the Reference Frequency
Voltage at Pin SI2 OPEN VCC GND OPEN VCC GND OPEN VCC GND SFref 36 33 48 65 63 64 35 32 49 Reference Oscillator Frequency 18.432 MHz - 24.576 MHz - - 32.768 MHz 17.920 MHZ 16.384 MHz -
Voltage at Pin SI1 GND GND GND OPEN OPEN OPEN VCC VCC VCC
3.8
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. By connecting a quartz crystal to pins OSCE and OSCB according to Figure 11-2 on page 16, this oscillator generates a highly stable reference signal. The ATR2731 (Atmel's one-chip front-end IC) offers the reference signal at pin FREF. This reference signal (LC filtered to suppress harmonics) can be used to overdrive the oscillator. In this application (see Figure 11-3 on page 16) the reference signal has to be applied to the pin OSCB and the pin OSCE must be left open.
3.9
Reference Divider
Nine different scaling factors of the reference divider can be selected by different voltage settings at the input pins SI1 and SI2: 32, 33(1), 35, 36, 48, 49(1), 63(1), 64, 65(1). The reference divider factors result in reference oscillator frequencies shown in Table 3-1.
Note: 1. These scaling factors result in an output frequency of the reference divider of 512 kHz. If harmonics of the Bd. 3 VCO fall in the L-band reception band, these spurious signals can influence the AGC of ATR2730, which could be a problem for small incoming signals. In this case it is possible to switch the reference divider from nref to nref + 1.
3.10
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section "Reference Divider" , the oscillator's frequency is controlled to be 1261.568 MHz in the locked state, and the output frequency of the RF divider is 512 kHz.
3.11
Phase Comparator, Charge Pump and Loop Filter
The tri-state phase detector causes the charge pump to source or sink current at the output pin PD depending on the phase relation of its input signals, which are provided by the reference and the RF divider respectively. Using the control pin CI, two different values of this current can be selected, and the charge-pump current can be switched off. The input of the high-gain amplifier (output pin CD), which is implemented in order to construct a loop filter as shown in the application circuit, can be switched to GND by means of the control pin CI (see Table 3-2 on page 8). In the application circuit, the loop filter is completed by connecting the pins PD and CD by an appropriate RC network.
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3.12
Lock Detector
An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control pin CI is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is deactivated and the logical value of the PLCK output is undefined.
3.13
Test Interface
If the input control pin CI is left open (high impedance state), a test signal, which monitors the output frequency of the reference divider, appears at the output pin TI. Analogous to the reference divider, a test signal monitoring the output frequency of the RF divider appears at the test interface output pin TI, if the input control pin CI is connected to VCC/2. Table 3-2.
CI GND Vs VCC/2 Open
Control Interface (CI) Settings
PD 200 A 300 A 0 A Connected to GND PLCK Ok Ok Undefined Undefined TI - - RF divider Reference divider
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ATR2730 [Preliminary]
4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage RF input voltage Voltage at pin AGC Voltage at pin TH Input voltage at pin TANK (internal oscillator overdriven) Current at IF output Reference input voltage (diff.) Control input voltage PLCK output current PLCK output voltage Junction temperature Storage temperature Pins 3, 9, 20 and 28 25 and 26 18 17 5 19 15 1, 2, 10 and 27 14 14 Symbol VCC VRF VAGC VTH VTANK IIF OSCB CI, SI1, SI2, PD IPLCK VPLCK Tj Tstg Value Unit V mVpp V V Vpp mA Vpp V mA V C C
-0.3 to +9.5
750 0.5 to 6
-0.3 to +4.0
1 4.0 1
-0.3 to +9.5
0.5
-0.3 to +5.5
125
-40 to +125
5. Operating Range
Parameters Supply voltage Ambient Temperature Pins 3, 9, 20 and 28 Symbol VCC Tamb Value 8 to 9.35 Unit V C
-40 to +85
6. Thermal Resistance
Parameters Junction ambient SSO28 (mod.) Symbol RthJA Value 50 Unit K/W
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7. Electrical Characteristics
Operating conditions: VCC = 8.5V, Tamb = 25 C unless otherwise specified. (See application circuit Figure 10-3 on page 15.) No. Parameters 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 4 4.1 4.2 4.3 5 5.1 Supply current (max. gain) Supply current (min. gain) Supply current (power-save mode) Amplifier Mixer Pin 26 Maximum conversion gain Minimum conversion gain AGC range Third-order 2-tone intermodulation ratio DSB noise figure (50 system) RF Input Frequency range Maximum input power Input impedance IF Output Frequency range Output impedance Voltage standing wave ratio Gain Control Threshold adjustment External resistor pRF = -10 dBm VAGC = 3.5V pRF = -60 dBm VAGC = 3.5V pRF = -10 dBm pRF = -60 dBm 18 18 5 fLO 1 kHz distance VCO overdriven, see "Application Circuit" (Figure 10-3 on page 15) L1kHz pLO,MIN pLO,MAX 1000 1261.568 1500 MHz dBc/Hz dBm dBm C C C 17 18 RTH ICP,P ICP,N VAGCmin VAGCmax 5.5 75 100 100 125 k A A V V D A A A A 19 fout,IF Zout,IF VSWRIF 150 50 2.0 250 MHz C D D dim3 20 dB pRF1 + pRF2 = -10 dBm pRF1 + pRF2 = -15 dBm Maximum gain Minimum gain 26 fin,RF pin,max,RF Zin,RF 1400 1550 MHz dBm || pF C C D pRF = -60 dBm pRF = -15 dBm Test Conditions pRF = -60 dBm VPSM < 0.5V pRF = -10 dBm VPSM < 0.5V pRF = -10 dBm VPSM > 2V 26 19 gc,max gc,min gc dim3 NF 28 30 35 20 24 dB dB dB dB dB dB dB A B A B A D Pin Symbol IS,MAX IS,MIN IS,PD Min. Typ. 40 41 20 Max. 48 50 24 Unit mA mA mA Type* A B A
-8
32 35 40 10 30
-6
200 || 1
5.2
Charge pump current
-125
-100
0.1 5.75
-75
0.6
5.3 5.4 6 6.1 6.2 6.3 6.4 7 7.1
Minimum gain control voltage Maximum gain control voltage VCO Frequency Phase noise Minimum input power Maximum input power Frequency Synthesizer RF divide factor
-75 -11 -5
SF
2464
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10
ATR2730 [Preliminary]
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ATR2730 [Preliminary]
7. Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5V, Tamb = 25 C unless otherwise specified. (See application circuit Figure 10-3 on page 15.) No. Parameters Test Conditions SI1 = GND, SI2 = GND SI1 = GND, SI2 = VCC SI1 = GND, SI2 = open SI1 = VCC, SI2 = GND SI1 = VCC, SI2 = VCC SI1 = VCC, SI2 = open SI1 = open, SI2 = GND SI1 = open, SI2 = VCC SI1 = open, SI2 = open 15 15 Single-ended Pin CI connected to GND 8.1 8.2 8.3 8.4 9 9.1 9.2 10 10.1 10.2 Input voltage 10.3 11 11.1 11.2 11.3 11.4 12 Test Interface TI Pin CI open Pin CI = VCC/2 Rload 1 M, Cload 15 pF, Pin CI open or VCC/2 1 PSM not active PSM active VPSM VPSM 2.0 0.6 V V A A 12.1 Reference test frequency 12.2 LO test frequency 12.3 Voltage swing 13 13.1 13.2 Power-save Mode PSM Input voltage Control Input CI Pin connected to GND Pin connected to VCC/2 Pin open Pin connected to VCC 11 ftest,ref ftest,LO Vsw 512 512 400 kHz kHz mVpp B B C Charge-pump current Output voltage PD Internal reference frequency Typical tuning voltage range Lock Indication PLCK Leakage current Saturation voltage Control Inputs SI Pin connected to GND Pin open Pin connected to VCC 10 VL VM Vopen VH 0.9 0 0.5 Open 1 VCC 0.1 VCC VCC A A A A VPLCK = 5.5V IPLCK = 0.25 mA 2 and 27 VL VM VH 0.9 0 Open 1 VCC 0.1 VCC A A A 12 14 IPLCK VPLCK,sat 10 0.5 A V A A Pin CI connected to VCC Pin CI connected to VCC/2 Pin CI open 13 13 Pin Symbol Min. Typ. 48 33 36 49 32 35 64 63 65 5 300 2.7k || 2.5 160 240 200 300 240 360 100 0.3 512 0.3 5 50 30 MHz mVrms mVrms k || pF A A nA V kHz V Max. Unit Type*
7.2
Reference divide factor
SFref
A
7.3 7.4 7.5 7.6 8
Input frequency range Input sensitivity Maximum input signal Input impedance Phase Detector
fref Vrefs Vrefmax Zref IPD2 IPD1 IPD1,tri VPD fPD Vtune
C C C D A A A A B C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. Gain Control Characteristics
Operating conditions: VCC = 8.5V, Tamb = 27 C, fRF = 1490 MHz, FLO = 1261.568 MHz Figure 8-1. IF Output Power (Pin 19)
-10
-15
-20
pIF (dBm)
-25 Rth = 100 k -30
-35
-40 -60 -50 -40 -30 -20 -10 0
pRF (dBm)
Figure 8-2.
Gain Control Voltage (Pin 11)
6
5 Rth = 100 k 4
VAGC (V)
3
2
1
0 -60 -50 -40 -30 -20 -10 0
pRF (dBm)
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ATR2730 [Preliminary]
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ATR2730 [Preliminary]
9. Phase-noise Performance
Measurement conditions: Values acquired at pin 19 with HP 70000 spectrum analyzer. RF input (pin 26) is blocked with 100 pF to GND. A low phase-noise signal generator (Marconi(R) 2042) was taken as PLL reference. Figure 9-1. Phase-noise Performance Operating Conditions: fREF = 17.92 MHz, -10 dB, IPD = 200 A
RL -29.29 dBm ATTEN 10 dB 10.00 dB/DIV
< -75 dBc/Hz
Center 1.261 568 GHz RB 100 Hz VB 100 Hz
Span 50.00 kHz ST 15.00 sec
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10. Equivalent Circuits
Figure 10-1. AGC Control Circuit
Gain controlled mixer Gain controlled amplifier
VRef1
550 MHz IF output 60 MHz VRef2
AGC
TH Rth
Figure 10-2. VCO Circuit
VTune 47 k BBY51 1.8 pF 15 pF Resonator 1 pF VREF 100 pF TANK VCC
Resonator: Ceramic coaxial resonator Murata(R) 3 x 3 mm, 1.6 GHz DRR030 KE1R600TC
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ATR2730 [Preliminary]
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ATR2730 [Preliminary]
Figure 10-3. Application Circuit
VAGC 3.3 F
+
8.5V 100 pF 100 pF 1 nF 10 nF 28 VCC4 27 SI1 26 RF 100 pF 10 nF 23 GND 22 GND 21 GND 20 VCC3 19 IF 100 pF 18 AGC 17 TH 16 OSCE 18 pF 33 pF 68 pF RF 8.5V 100 pF IF 1 nF 100 k Quartz crystal
25 NRF
24 GND
15 OSCB 14 PLCK
ATR2730
VCC1 VREF VCC2 TANK GND GND GND PSM SI2 CD 12 PD 13 CI 10 TI 11
Power save
1
2 100 pF
3
4 1 pF
5
6
7
8
9
5V
10 nF
10 nF 56 k
Lock indication
100 pF 1) 100 pF 8.5V 100 pF 8.5V 1 nF
1.8 pF
47 k 1 nF 15 pF
1 k 3.3 nF 1)
1 k 3.3 nF 1)
D1
1) optional
Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 A
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11. Application Circuit for External LO Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal VCO acts as an LO buffer. Figure 11-1. Application Circuit for External LO Signal
External LO signal (50 signal gen.) PLO = -10 dBM 50 TANK 100 pF 470 nH VREF 1 nF
Figure 11-2. Reference Oscillator Operation
68 pF OSCB Reference divider
33 pF Quartz crystal OSCE 18 pF
Figure 11-3. Reference Oscillator Overdriven
Reference signal L1 C1 OSCE OSCB Reference divider
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ATR2730 [Preliminary]
12. Ordering Information
Extended Type Number ATR2730-TLSY ATR2730-TLPY ATR2730-TLQY Package SSO28 SSO28 SSO28 Remarks Tube, Pb-free Taped and reeled according to IEC 286-3, 180 m size, Pb-free Taped and reeled according to IEC 286-3, 330 m size, Pb-free
13. Package Information
5.40.2 9.35-0.25 4.40.1
0.05+0.1
1.30.05
0.250.05 0.650.05 8.450.05
6.450.15
28
15
Package: SSO28 Dimensions in mm
technical drawings according to DIN specifications
1 Drawing-No.: 6.543-5056.03-4 Issue: 1; 10.03.04
14
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4903C-DAB-03/07 History * Put datasheet in a new template * Section 12 "Ordering Information" on page 17 changed
0.150.05
17
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4903C-DAB-03/07

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